6502 TXY Wishlist: Missing Instructions

1 March 2020 · Updated 26 February 2026

Speculation about hypothetical TXY and TYX instructions that MOS Technology could have included in the 6502 processor. Loading a zero page value into both index registers currently demands cumbersome solutions that consume precious cycles in timing-critical code.

Comparing Approaches

Conventional Method

6 cycles, 4 bytes consumed
Separately loads the zero page value into X then Y using LDX zpval followed by LDY zpval
Requires accessing the same memory location twice, which seems wasteful

LAX Illegal Opcode Method

5 cycles, 3 bytes consumed
LAX ZPVAL followed by TAY
Disadvantage: modifies the accumulator contents, which may need preservation
The LAX instruction loads a value into both A and X simultaneously, then TAY copies to Y

Hypothetical TXY Instruction

Would require only 5 cycles, 3 bytes (matching LAX but without accumulator side effects)
Leaves the accumulator untouched, preserving whatever calculation was in progress
Superior for timing-critical raster routines where accumulator contents must persist across operations

Other Desired Instructions

Immediate addressing mode for LAX, enabling direct loading of constants into A and X simultaneously
LAY (a Y-register equivalent to LAX) for loading into A and Y with one instruction
Combined LXY instruction loading the same value into both index registers, leaving A free

For seasoned assembly developers working on interrupt-driven code, even one-cycle improvements compound significantly across repeated operations. A raster effect triggering 200 times per frame, 50 frames per second, executes 10,000 times per second—saving one cycle saves 10,000 cycles per second, potentially enabling additional effects or smoother gameplay.